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Systems/Logisim Processor
43 / 67

11/2021Systems

Logisim Processor

A fully functional 16-bit CPU built in Logisim from bare gates — ALU, register file, micro-sequenced control, and memory-mapped IO, running real programs.

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A fully functional 16-bit CPU implemented in Logisim, built up from bare gates: the ALU, the register file, the control unit, the program counter, RAM, a micro-sequencer driven by a finite-state machine, and memory-mapped IO. It runs real programs, hand-assembled into its own 16-bit instruction encoding.

The 16-bit machine assembles whole: the PC addresses RAM; the fetched word lands in the instruction register and splits into fields; the register file feeds the ALU, which sets the flags; results write back down the inner right margin, and the next PC loops down the outer one. The micro- sequenced FSM (left) reads the opcode and drives a control word to every unit, one micro-step per clock.

Every part of the machine reduces to gates. The ALU's adder is a chain of full adders; subtraction is addition of the two's complement; comparisons fall out of the subtractor's sign and zero flags. Multiplexers built from AND/OR trees steer every bus, and each register is a rank of D flip-flops behind a write-enable. With select lines a multiplexer chooses among inputs; the machine is built by applying that identity at every scale.

The control unit is a finite-state machine that sequences each instruction over several clock cycles: fetch the word at the PC, decode its opcode, execute its micro-operations. The micro-sequencer walks a ROM of control words, one per state, asserting the right write-enables, bus selects, and ALU function bits, then jumps back to fetch. Adding an instruction means adding rows to that ROM, not rewiring the machine.

References

  1. Project repository
  2. Reference notes: The Fetch-Decode-Execute Cycle
  3. Reference notes: Multiplexers, Decoders, and the ALU
  4. Reference notes: Memory Elements: Latches, Flip-Flops, and Clocking

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